Chiplet architecture in 2026: overview
Chiplet architecture assembles a processor or other integrated circuit from multiple smaller dies connected inside a package. It lets designers combine different process technologies and functions, rather than forcing every component onto one monolithic die. That flexibility is especially relevant as AI and high-performance computing demand more compute, memory bandwidth and integration. The challenge is shifting from transistor scaling alone to system-level design, where packaging, interconnects, power, heat and test must work together.
Recent work targets the materials and engineering limits of that integration. In October 2026, Tsinghua University reported CMP-free all-copper bonding using porous copper, while Unimicron Technology Corporation examined glass packaging and Cu-Cu hybrid bonding. Research also addresses high-speed signal integrity, thermal-aware analysis and reliability; a September 2026 paper, GigaRDL, applies GPU-resident routing to redistribution layers. Meanwhile, UCIe and protocol work such as PCIe over UCIe and AMBA over UCIe focus on interoperable die-to-die links. Publications reached 585 last year, up 28.3%, as the field moves toward repeatable multi-die design and manufacturing.
- 1Packaging sets the pace: As chiplet systems grow more complex, bonding, interconnect reliability and thermal behavior increasingly shape what can be integrated in one package.
- 2Standards meet system design: UCIe and protocol work are extending die-to-die links from physical connectivity toward coherent, interoperable multi-die systems.
- 3Design tools move earlier: Signal-integrity, thermal and routing methods aim to expose package-level risks earlier, reducing costly iteration later in the design flow.
Top organizations working on chiplet architecture
Ranked by Linknovate activity score · last 24 monthsThe activity score adds up the relevance of every patent, publication, grant and news item linking an organization to chiplet architecture. Showing 7 of 414 organizations.
| # | Organization | Approach | Signals (24 mo) | Momentum | Why it matters |
|---|---|---|---|---|---|
| 1 |
Intel Corporation
Corporate · United States |
Die-to-die interfaces | PAT 95 · PUB 39 NEWS 765 |
-31% | Intel develops chiplet interconnect technology and has published work on UCIe, an open standard for connecting dies through planar and vertical on-package links. |
| 2 |
TSMC
Corporate · Taiwan |
2.5D interposer | PAT 6 · PUB 15 NEWS 544 |
-32% | TSMC researches high-bandwidth chiplet interconnects and advanced packaging, including signal integrity and reliability challenges in 3D chiplet stacks. |
| 3 |
Siemens AG
Corporate · Germany |
General | PUB 10 · GRANTS 1 NEWS 483 |
+4% | Siemens EDA develops design and verification tools for multi-die systems, including workflows for managing chiplet integration and checking die-to-die protocol behavior. |
| 4 |
Advanced Micro Devices Inc.
Corporate · United States |
Composable die partitioning | PAT 25 · PUB 10 NEWS 557 |
-37% | AMD builds processors from multiple dies and explores chiplet-based system designs, including approaches to on-package memory and high-bandwidth interconnect. |
| 5 |
Synopsys Inc.
Corporate · United States |
3D die stacking | PUB 5 · NEWS 358 | +297% | Synopsys develops EDA tools and semiconductor IP for chiplet design, verification, and test, including validation of high-speed links in stacked multi-die systems. |
| 6 |
Cadence
Corporate · United States |
Die-to-die interfaces | PUB 3 · NEWS 265 | +8% | Cadence provides chiplet design and verification tools and has published die-to-die transceiver work for UCIe links in advanced and standard packages. |
| 7 |
Samsung
Corporate · South Korea |
Die-to-die interfaces | PAT 19 · PUB 12 NEWS 321 |
-32% | Samsung develops semiconductor and packaging technologies for multi-die systems; its patent work includes transmitting memory-interface signals between dies using UCIe. |
| 8 | ··Hidden organizationCompany | Approach | PAT 00 · PUB 00 GRANTS 0 · NEWS 00 | +00% | Available to registered users. |
| 9 | ··Hidden organizationCompany | Approach | PAT 00 · PUB 00 GRANTS 0 · NEWS 00 | +00% | Available to registered users. |
| 10 | ··Hidden organizationCompany | Approach | PAT 00 · PUB 00 GRANTS 0 · NEWS 00 | +00% | Available to registered users. |
Startups to watch and leading research centers
Startups to watch 15 total
Lightmatter Inc.United StatesLightmatter is developing photonic interconnects for high-bandwidth chiplet systems, including patents for 3D-stacked I/O dies and optical interposers.
Rebellions IncSouth KoreaRebellions develops AI accelerators and has patented chiplet communication, latency measurement, and secure boot methods for multi-chiplet systems.
Celestial AiUnited StatesCelestial AI is developing photonic chiplet interconnects; its patents describe optical bridges and hybrid electro-photonic platforms for high-bandwidth data movement.- ··Hidden startupCountryAvailable to registered users, with funding and founding year.
- ··Hidden startupCountryAvailable to registered users, with funding and founding year.
Leading research institutions 263 total
IMECBelgiumimec researches chiplet interconnect testing and repair for 2.5D and 3D systems, and coordinates industry collaboration on automotive chiplet architectures.
Massachusetts Institute of TechnologyUnited StatesMIT researchers have demonstrated integration of a diamond waveguide micro-chiplet with a cryogenic CMOS controller for photonic readout in quantum processors.
Georgia Institute of TechnologyUnited StatesGeorgia Tech researchers develop tools and methods for 2.5D chiplet architectures, including interconnect simulation, thermal prediction, and packaging-aware design.- ··Hidden research institutionCountryAvailable to registered users, with their key researchers.
- ··Hidden research institutionCountryAvailable to registered users, with their key researchers.
Where chiplet architecture innovation happens
Share of documents with at least one organization from each country.
Open the interactive map with all 414 organizationsMain technical approaches
Last 24 months| Approach | What it is | Documents | Leading organizations |
|---|---|---|---|
| 2.5D interposer | Places dies side by side on an interposer for dense connections; it offers high bandwidth but adds interposer cost and package complexity. | 371 |
Intel Corporation, SOC, TSMC |
| 3D die stacking | Stacks dies vertically for compact, short connections; it can improve density and bandwidth but makes heat removal and test more difficult. | 773 |
Intel Corporation, TSMC, Siemens AG |
| Bridge-based integration | Uses small bridges to connect nearby dies; it can reduce reliance on a full interposer but constrains placement and routing. | 219 |
Intel Corporation, TSMC, Socs |
| Fan-out integration | Embeds dies in a reconstituted wafer and routes connections through redistribution layers; it can reduce package size but requires careful warpage and yield control. | 583 |
TSMC, Intel Corporation, Advanced Micro Devices Inc. |
| Die-to-die interfaces | Defines the electrical and protocol links between dies; standardization can improve interoperability but does not remove package-level signal, power or security challenges. | 584 |
Intel Corporation, SOC, EDA Inc. |
| Composable die partitioning | Divides a system into reusable functional dies; it supports modular design but makes partitioning, interface compatibility and system validation harder. | 165 |
Intel Corporation, Advanced Micro Devices Inc., TSMC |
Emerging trends
Last 12 months vs previous 36 monthsTerms whose frequency in the last 12 months grew the most compared with the previous 36 months.
Funding and investment
Recent funding rounds
Grant activity totals $1,188,461,269 across 82 grants since 2020. Funding-round records aggregate $1,154,369,657,666 across 69 rounds, but examples mix chip-related financing with broader infrastructure and AI investments, so treat that figure as a noisy indicator rather than dedicated chiplet capital.
Patent landscape
Top patent holders · last 24 monthsRecent developments
Latest news, duplicates removed- Oct 2026Observe how protocol intent becomes die-to-die activity and how link-state transitions affect transaction behavior. By Kartik Sahajpal and Prashant Dixit Chiplet-based architectures are reshaping how high-performance…Semiconductor Engineering
- Sep 2026Transforming established SoC design paradigms into system-level fabrics capable of supporting next-generation AI, HPC, and data center workloads. As computing systems evolve to meet the demands of AI, data centers, and…Semiconductor Engineering
- Sep 2026The Universal Chiplet Interconnect Express (UCIe) is designed to connect chiplets together, providing multiple high-speed serial interfaces (see figure). The standard is from the UCIe Consortium, with its latest…Home | Electronic Design
- Jul 2026Heterogeneous integration does not simply increase complexity but redistributes where quality must be assured. AI drives demand for xPU [1], HBM, switches, and CPO, but lithographic limits mean monolithic dies can’t…Semiconductor Engineering
- Month 20XXHidden developmentAvailable to registered users with alerts enabled.
Frequently asked questions about chiplet architecture
What companies are working on chiplet architecture?
Intel Corporation, TSMC, Advanced Micro Devices Inc., Qualcomm, Samsung and Siemens AG are among the companies active in chiplet architecture. Their work spans die-to-die links, advanced packaging, processor designs and multi-die design tools. Cadence and Synopsys Inc. also develop design and verification tools, while Arm Ltd. is working on its Chiplet System Architecture.
Which chiplet architecture startups are the most promising in 2026?
Lightmatter Inc., Rebellions Inc and Celestial Ai are notable startups pursuing distinct chiplet approaches. Lightmatter and Celestial Ai focus on photonic interconnects, while Rebellions develops AI accelerators and has patented chiplet communication and security methods. Their focus areas point to opportunities in high-bandwidth data movement and multi-chiplet systems, though their approaches address different technical needs.
Which universities and research centers lead chiplet architecture research?
IMEC, Massachusetts Institute of Technology and Georgia Institute of Technology are prominent research organizations in this field. IMEC works on interconnect testing and repair for 2.5D and 3D systems. MIT has researched photonic chiplet integration for quantum processors, while Georgia Tech develops interconnect simulation, thermal prediction and packaging-aware design methods.
How much funding has chiplet architecture received?
FACTS records $1,188,461,269 in grants across 82 awards since 2020. This is the clearest dedicated grant indicator provided, but it should not be read as total investment in chiplet technology. The funding-round records aggregate $1,154,369,657,666 across 69 rounds and include broad AI and infrastructure financing, making that total a noisy measure of chiplet-specific funding.
Who holds the most chiplet architecture patents?
Intel Corporation leads the listed patent holders with 95 patents, followed by Qualcomm with 60 and Unifabrix Ltd. with 30. Advanced Micro Devices Inc. has 25, and Robert Bosch GmbH has 23. These figures identify organizations with substantial patent activity in the dataset; they do not by themselves establish the quality, scope or commercial use of those patents.
Is chiplet architecture patent activity growing?
Patent activity declined 44.0% in the latest 12-month period, with 755 patents in the 24-month window. Publication activity moved in the opposite direction: 585 publications appeared last year, up 28.3%. The split suggests research output is rising even as patenting has slowed, but neither measure alone establishes whether a technology is ready for broad commercial adoption.
What are the latest developments in chiplet architecture?
October 2026 work from Tsinghua University reported CMP-free all-copper bonding using porous copper, while Unimicron Technology Corporation examined glass packaging and Cu-Cu hybrid bonding. Recent research also addresses signal integrity, thermal analysis and package routing. In September 2026, GigaRDL proposed GPU-resident routing for redistribution layers, reflecting efforts to make complex package design more efficient.
What are the main approaches in chiplet architecture, and how do they differ?
The main approaches include 2.5D interposers, 3D die stacking, bridge-based integration, fan-out integration, die-to-die interfaces and composable die partitioning. Interposers and bridges connect side-by-side dies; stacking places dies vertically. Fan-out uses redistribution layers, while interface standards define how dies communicate. Each approach trades off bandwidth, package complexity, thermal behavior, routing flexibility and testability.
Which countries lead chiplet architecture?
The United States leads with 9,973 documents, followed by Germany with 2,369 and Taiwan with 1,984. The United Kingdom, China and South Korea are also active, with 1,914, 1,669 and 1,607 documents respectively. These figures indicate where activity is concentrated in the dataset, not necessarily where all chiplet manufacturing or supply-chain capacity is located.
What are the applications of chiplet architecture?
AI and high-performance computing lead the listed applications with 3,983 documents, followed by automotive computing with 3,512. Other areas include consumer and mobile electronics, quantum computing, and networking and communications. Chiplets can combine compute, memory and specialized functions in one package, but each application brings different requirements for performance, power, reliability, cost and system validation.